Encoder is a digital circuit in which the performed operation is exactly the opposite of decoders. An encoder consists of a maximum of 2n inputs and produces binary code corresponding to input data as ‘n’ number of outputs. At any instant, among 2n inputs, only one input is HIGH (i.e., logic 1); otherwise circuit has no meaning.


The below-given block diagram shows that the encoder can take any no. of inputs and give many outputs. For each input code, only one output is high. Let say m= no. of inputs and n= no. of outputs, then m ≤ 2n or n = log2m.
The encoders are used to convert the specific codes into the binary code such as:-
In an 8-to-3 line encoder, there is an input for each of the octal digits. It has eight numbers of inputs, which generates the corresponding binary number and has three outputs. At any instant in time, only one input is high. In case two of the inputs are HIGH simultaneously, the encoder will establish the priority accordingly, so that only one input is encoded at any given time. The encoder can be realized using the OR gates.
Truth table
From the above truth table, we obtain that:-
O0 = I1 + I3 + I5 + I7
O1 = I2 + I3 + I6 + I7
O2 = I4 + I5 + I6 + I7
The 10-to-4 line encoder takes ten inputs and transmits the information into corresponding BCD code, having four outputs.
Truth table
From the above truth table, we obtain that:-
O0 = I1 + I3 + I5 + I7 + I9
O1 = I2 + I3 + I6 + I7
O2 = I4 + I5 + I6 + I7
O3 = I8 + I9
The priority encoder is a modified version of a conventional encoder. It eliminates all the limitations that existed with a simple encoder. One of the limitations occurs when more than one input is activated at any instant in time. The priority encoder has the priority function. The priority encoder performs necessary logic to ensure that when two inputs or more inputs are activated simultaneously, the output code will correspond to the “highest-number input.”


The truth table for 4-input priority encoder
Simplified Boolean expression
O0 = I2 + I3
O1 = I3 + I1 I2
O2 = I0 + I1 + I2 + I3
Logic diagram for 4-bit priority encoder
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